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CAES, a leader in advanced mission-critical electronics for aerospace and defense, announced that it has been awarded a contract from Vinnova, a Swedish government agency dedicated to promoting innovation, to develop next generation RISC-V based space computing capabilities. The results from this development will allow future CAES microprocessors to enable spacecraft control, create high performance payload processing and will feature timing isolation for software applications and prevent interference from other parts of the system.
The new NOEL-V fault-tolerant, 64-bit processor core is based on the open RISC-V instruction set architecture and builds upon CAES’ heritage with the SPARC/LEON architecture. It marks the newest addition to CAES’ trusted fault tolerant space computing product portfolio.
“We look forward to working with Vinnova and our project partners to enhance our RISC-V processor technology to meet our customers’ next generation space program needs,” said Mike Kahn, President and CEO of CAES. “Our space systems team is fully prepared to address the market’s growing need for cybersecurity and create the next generation of trusted, radiation hardened processors with both RISC-V and SPARC/LEON architectures to enable low risk, high performance implementation for space applications.”
“The results of this initiative with Vinnova will inform our future radiation-hardened NOEL-V microprocessor development in collaboration with the European Space Agency,” said Sandi Habinc, General Manager of Gaisler Products, CAES. “Our team plans to publish the results and disseminate the technology to benefit the industry at large.”
Once complete, a multi-core NOEL-V processor development platform will be tested through a partnership with Chalmers University of Technology and atsec, an independent laboratory focused on information security, to ensure utmost security towards higher software layers.
“Chalmers’ collaboration on the LEON processor development dates back to 1997," said Stefan Bengtsson, President and CEO of Chalmers University of Technology. “We are excited to continue this long-standing collaboration on the RISC-V processor architecture as part of the Vinnova activity.”