Stephen Chavez and Happy Holden on Designing Reliable Vias


Reading time ( words)

Andy Shaughnessy and Happy Holden speak with Stephen Chavez, a staff engineer with an aerospace company and chairman of the Printed Circuit Engineering Association (PCEA), about designing vias for greater reliability. They also address several areas where they can look to improve reliability, a variety of steps that designers should take to help ensure more robust vias, and some testing and educational resources that PCB designers and design engineers should be aware of.

Andy Shaughnessy: Welcome, gentlemen. Companies keep having problems with vias. Some OEMs will send out a dozen test boards with different-sized vias to a dozen different fabricators, and they’ll come back built a dozen different ways. What can the designers do? What are your thoughts on via design for reliability?

Stephen Chavez: My initial thought on this is that at the earliest stages of the design cycle, communication with your suppliers is an extremely important part of your overall PCB design success. Collaborating with your supplier to lock in your PCB stackup is also a vital step in the early stages of your design. This leads to solidifying your constraints before parts are placed and any traces are routed, which includes the types of via technology that will be implemented in the design. By collaborating with your suppliers and applying industry best practices for PCB design, the odds of achieving a robust, high-reliability DFM design is very good.

As today’s printed circuit engineers strive to meet today’s challenges, there are three competing perspectives for success when designing PCBs: design for layout solvability (DFS); design for performance (DFP), meaning SI/ EMC, power delivery, and thermal; and design for manufacturability (DFM). In the end, the main goal is to get it right the first time. Make Revision 1 work by maximum placement and routing density, optimum electrical performance, and efficient, defect‐free manufacturing to achieve high yield and lower cost.

When I talk about meeting today’s challenges when designing multilayer PCBs while keeping in mind the three competing perspectives for success, the via strategy and quality of the via structure is very important. No matter which via technology you utilize in your design—whether it is standard PTH, HDI, microvias, or a combination of the three—you want it designed so that the via is in the board fabricator’s sweet spot while meeting your design requirements and DFM for downstream optimization. If you’re not doing that, you’ll be having a lot of problems. I am still surprised to find there are many people who aren’t talking to their suppliers, and they’re just throwing the design over the fence.

Then, you have to understand the material you’re choosing. Are you choosing the right material for your application and the widget that you’re building? Are you designing in the core sweet spots for success, or are you pushing the rail on complexity? You had better be speaking and understanding the industry terminology and language when talking to your supplier to make sure that you’re on the same page so that there are no surprises at the end.

Happy Holden: If an OEM is naïve enough to send a board out to multiple vendors, they shouldn’t be surprised that they’ll come back different because every fabricator optimizes drilling, desmear, metallization, and plating to be as reliable as they can possibly make it. But because of the multiple vendors, machines, and processes, there are 10,000 different permutations and combinations that make up every multilayer. An OEM deserves whatever they lose if that’s the way they’re going to manage their supply chain. They should develop a qualification process that’s statistically significant, but they won’t, and the fabricators won’t tell them that they’re foolish.

To read this entire interview, which appeared in the November 2020 issue of Design007 Magazine, click here.

Share

Print


Suggested Items

Why We Simulate

04/29/2021 | Bill Hargin, Z-zero
When Bill Hargin was cutting his teeth in high-speed PCB design some 25 years ago, speeds were slow, layer counts were low, dielectric constants and loss tangents were high, design margins were wide, copper roughness didn’t matter, and glass-weave styles didn’t matter. Dielectrics were called “FR-4” and their properties didn’t matter much. A fast PCI bus operated at just 66 MHz. Times have certainly changed.

Bridging the Simulation Tool Divide

04/12/2021 | I-Connect007 Editorial Team
Todd Westerhoff of Siemens EDA recently spoke with the I-Connect007 Editorial Team about the divide between users of high-powered enterprise simulation tools and those who need a more practical tool for everyday use, and how Siemens is working to bridge the gap. Todd also shared his views on why so many engineers do not use simulation, as well as advice for engineers just getting started with simulation tools.

Barry Olney’s High-Speed Simulation Primer

04/09/2021 | I-Connect007 Editorial Team
The I-Connect007 editorial team recently spoke with Barry Olney of iCD about simulation. Barry, a columnist for Design007 Magazine, explains why simulation tools can have such a steep learning curve, and why many design engineers are still not using simulation on complex high-speed designs.



Copyright © 2021 I-Connect007. All rights reserved.