Designers Notebook: Panel-level Semiconductor Package Design Challenges

Semiconductor package specialists continually work to improve high-volume manufacturing process efficiencies while reducing manufacturing costs. A majority of the commercial semiconductors are built-up on the surface of a circular-shaped silicon wafer with metalized terminal features at their perimeter to accommodate wire-bond interface with a lead-frame or package substrate. To enable direct, face-down mounting to a package substrate or host PCB, the aluminum wire-bond sites on these products must first be processed to provide an alloy (typically copper) that will accept traditional solder ball or bump termination features.

When die have a perimeter terminal spacing that is considered too close for efficient circuit routing, it is common practice to employ an additive metalization process on the active surface of the die to provide a conductive interface from the wire-bond lands at the die elements perimeter to a wider-spaced and more uniform array configured terminal pattern.

Solberg_fig1_0520.jpgCommonly referred to as fan-in, wafer-level package (WLP), the process for adding a metalized redistribution layer (RDL) connecting the original wire-bond lands to an array-configured terminal feature is accomplished while the die elements remain in the original silicon-based wafer format (Figure 1). 

While the majority of the semiconductors selected for face-down interconnect can utilize the RDL processes noted, an expanding number of small-outline, very-high I/O, silicon-based processors are really not suited for conventional fan-in RDL processing. 
 
Fan-out, Wafer-level Packaging (FOWLP)
The most practical solution for mounting and interconnecting very-high I/O, small-outline die to a substrate or PCB is to expand the terminal pattern outward. The process commonly utilizes a prepared silicon wafer base with metalized RDL designed to mount and interconnect the higher density die element to an array-configured terminal feature is outside the perimeter of the die. Metalization provided on the silicon wafer base redistributes the terminal features on each die to a pattern of plated micro-via holes that interfaces with metalized land pattern features on the opposite surface of the wafer (Figure 2). 
Solberg_fig2_0520.jpg
The die elements terminated on the wafer’s upper surface are frequently encased with a polymer mold compound followed by solder ball or bump terminal formation, marking,  
and singulation to enable unit-level electrical testing. 
 
Fan-out, Panel-level Packaging (FOPLP)
The semiconductor package development specialists are always striving to find solutions for improving manufacturing efficiency and trim manufacturing costs. Although the FOWLP process has proved robust and reliable, the cost associated with silicon-based interposer fabrication has been a primary roadblock. In the effort to trim overall packaging expense, a number of alternative packaging methodologies have emerged. Both independently and through consortia between academia and industry, several viable solutions have evolved that provide the same fan-out interface without the need for a silicon wafer as a base. 
 
Panel-level package development utilizing alternative, lower-cost base materials actually began prior to 2016 to address several high volume market segments. By 2019, four prominent supply sources in Asia—Powertech, Samsung, and Nepes—had already achieved volume-manufacturing capability followed by ASE Group beginning production in early 2020. The timetable for additional offshore and domestic companies’ availability of FOPLP in volume is forecast for 2021 and 2022. 
 
FOWLP vs. FOPLP
When compared to the silicon-based FOWLP, developers implementing the panel-configured process have realized significant cost savings, greater process efficiency, and the economies of scale. Equating the high material cost of silicon wafers to the significantly lower-cost panel material is a key issue, but the greater die population potential for panel-level processing has proved most beneficial. 
 
In regard to establishing standards for the basic panel structure, several manufacturers and material supplier members of SEMI (Semiconductor Equipment and Materials International) 3D Packaging and Integration Technical Committee have developed SEMI 3D20-0719, which is a specification for panel characteristics for panel-level packaging (PLP) applications. The organization’s position is that “standards increase industry efficiency by reducing or eliminating duplication of efforts, help to define new markets, and promote competition by lowering barriers to entry.”
 
The purpose and scope for the SEMI PLP specification were written to include four process-compliant base materials for carrier panels and establish standard panel dimensions. Revision A of the document (currently submitted for member approval) establishes two standard panel sizes: 510 mm x 515 mm (~ 20” x 20.3”) and 600 mm x 600 mm (~ 23.6” x 23.6”). The four optional base materials noted for carrier panel preparation are glass, silicon, ceramic, and metal; however, silicon and ceramic materials have a significantly higher material cost. 
 
The semiconductor-packaging specialists will select the material and panel size that will best meet their particular assembly, molding system, and plating process capability. In regard to panel size, the half-panel may be more suitable for processing within the commercial circuit board manufacturing environment while a quarter-panel size will likely be most compatible with semiconductor wafer processing specialists currently utilizing systems configured to handle the 300 mm silicon wafer format.
 
In a presentation by Fraunhofer IZM[1] at a recent International Electronics Commission (IEC) standards meeting in Japan, the speaker noted several key drivers supporting FOPLP technology:  

  • Reduced overall package form factor 
  • A thinner package profile
  • Improved electrical performance 
  • Enhanced thermal management 
  • The potential for greater component integration and design flexibility 

The packaging process variations described in the Fraunhofer presentation primarily focused on a mold-first procedure where the singulated die elements are placed, with the active surface face-up or face-down, onto the carrier panel that is pre-coated with an adhesive. 
 
Mold-first FOPLP
Following die placement, the populated  
carrier panel is overmolded with a reinforced polymer compound, fully encasing all die  
elements. The material selected for the carrier panel must closely match the CTE of the silicon-based die elements (2.3 ppm/K) to minimize the occurrence of die shift during the mold cure process, 

  • Face-down FOPLP: After mold cure, the encased die elements are separated from the carrier panel exposing the active surface of the die elements. Surface metalization follows with pattern plating from the die terminal sites to a fan-out terminal pattern (Figure 3a). 
  • Face-up FOPLP: The overmolded die elements mounted in the face-up orientation (Figure 3b) is somewhat more complex because it requires the removal of the polymer mold material to expose the terminal features for surface metalization and circuit pattern plating typical of that described above.

Solberg_fig3_0520.jpg
The final process sequence for both process variations includes terminal formation (typically a solder-compatible alloy ball or bump), marking, saw or laser singulation, and package-level electrical test. 
 
For very fine pitch (>3.0 mm) applications, the developer may employ a secondary selective plating process to form raised, solid copper terminals. The so-called “micro pillar” is significantly smaller in diameter than the ball or bump variations, enabling a considerably narrower ( 
Solberg_fig4_0520.jpgMultiple-die FOPLP
Other process variations have naturally evolved, including multiple-die configurations. The benefit of clustering and interconnecting two or more associated heterogeneous or homogenous semiconductor die within the confines of a single package outline enables very close coupling and the potential for enhanced electrical performance (Figure 4). 
 
The target package outline for a broad number of wearable and wireless products is 100 mm2 to 140 mm2. Ideally, the die elements selected for both single and multiple-die applications will be able to achieve equivalent finished package outline goals while maintaining the uniform terminal pattern required for efficient PCB-level circuit routing. Although the interconnect design process may initially remain within the package developer organizations, PCB design specialists will likely have the opportunity to contribute their talents as well, especially in developing the multiple-die FOPLP configurations. 
 
Design Rules for FOPLP
In regard to design rules for single and multiple-die package applications, those currently familiar or becoming familiar with high-density additive and semi-additive circuit design criteria will be prepared to put their talents to good use. It’s really a matter of scaling. The design guidelines furnished in Table 1 illustrate the expectations for interconnecting semiconductor die in the FOPLP format.
 
Because process capabilities will often vary between one supplier or another, the circuit density and feature sizes noted in Table 1 may be more or less than those factors shown. Before beginning the development of the fan-out circuit interconnect pattern, the designer is advised to confirm compliance with the manufacturer’s imaging and plating capability.

Solberg_fig5_0520.jpg
 
Qualification Testing
With shorter development cycle time and more frequent introduction of new package technologies, a comprehensive qualification methodology will remain paramount in order to identify reliability weaknesses during the qualification of new package variations and material sets. A study by members of iNEMI (International Electronics Manufacturing Initiative) consortia[2] concluded that “New integrated circuit package technologies can be qualified using procedures and test conditions based on experience with similar technology previously qualified.” 
 
For example, semiconductor package developers are currently applying established JEDEC standards that basically require the end-product to be subjected to three solder reflow cycles at 260°C for preconditioning followed by 1,000 cycles through temperatures that range between –40°C and +125°C, as well as a highly accelerated temperature and humidity stress test (HAST) lasting 96 hours at 121°C with 85% relative humidity. Some experts, however, are concerned that current test standards may not identify reliability risks for all commercial-use environments. The iNEMI study noted, “While previous experience is important to consider, it cannot be the only criterion and relying too much on past experience may result in overlooking new failure modes and/or new wear-out mechanisms.”
 
In regard to package manufacturing process refinement, reaching satisfactory levels of throughput while maintaining quality objectives are not trivial issues. Developers have had to overcome a number of obstacles for each process variation. Matters that needed to be resolved include the selection of the most suitable carrier panel material, achieving precise die placement capability, dealing with mold material shrinkage and die shifting during the mold curing process, overcoming panel warping during the metallization process, and defining the most robust die thickness and mold cap thickness ratio.   
 
References
1. Dr. Tanja Braun, “Status FOPLP,” Fraunhofer IZM, Germany.
2. C. Grosskopf, F. Xue, D. Locker, S. Thomas, J. Zheng, & M. Tsuriya, “Benchmarking of Qualification Methodologies for New Package Technologies and Materials,” 2019  
International Conference on Electronics Packaging (ICEP), Niigata, Japan, 2019, pp. 1–6.
 
This column originally appeared in the May 2020 issue of Design007 Magazine.

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2020

Designers Notebook: Panel-level Semiconductor Package Design Challenges

05-15-2020

Semiconductor package specialists continually work to improve high-volume manufacturing process efficiencies while reducing manufacturing costs. A majority of the commercial semiconductors are built-up on the surface of a circular-shaped silicon wafer with metalized terminal features at their perimeter to accommodate wire-bond interface with a lead-frame or package substrate. Vern Solberg explains.

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Designers Notebook: Design Challenges for Developing High-density 2.5D Interposers, Part 2

01-29-2020

In Part 2 of his column series on design challenges for high-density 2.5D interposers, Vern Solberg discusses primary base materials for 2.5D interposer applications, design guidelines, technical challenges, and key planning issues.

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Designers Notebook: PCB Design and HD Semiconductor Packaging

01-15-2020

To better meet their performance and miniaturization goals, manufacturers are looking for higher functionality for their semiconductor packages. For that reason, many manufacturers will rely heavily on more innovative IC package solutions, often integrating a number of already proven functional elements within a single-package outline. Vern Solberg covers how this and more impact PCB design and HD semiconductor packaging.

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2019

Designers Notebook: Focus of Interest at SMTAI 2019—Low-temperature Solder

10-03-2019

Both suppliers and users of solder materials participated in discussions at SMTAI 2019 related to low-temperature solder (LTS). The solder supply companies present had a wide range of material compositions that employed elements of bismuth or indium to reduce the liquidus temperature of the alloy during the joining process. Key issues that user companies are concerned with are the lower-temperature alloys selected must be reliable and exhibit shear strength, creep resistance, and resistance to thermal fatigue for the duration of the product’s life cycle.

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Designers Notebook: Embedding Components, Part 7—Semiconductor Placement and Termination Methodologies

03-11-2019

Progress in developing high-density embedded-component substrate capability has accelerated through the cooperation and joint development programs between many government and industry organizations and technical universities. In addition to these joint development programs, several independent laboratories and package assembly service providers have developed a number of proprietary processes for embedding the uncased semiconductor elements.

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Embedding Components, Part 6: Preparation for Active Semiconductor Elements

01-10-2019

Designers are well aware that a shorter circuit path between the individual die elements, the greater the signal transmission speed, which significantly reduces inductance. By embedding the semiconductors on an inner layer directly in line with related semiconductor packages mounted on the outer surface, the conductor interface distance between die elements will be minimized.

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2018

Embedding Components, Part 5: Alternative Termination Methodologies and Surface Plating Variations

12-19-2018

Because they are furnished with a very thin profile, resistor and capacitor components with different values can be mounted directly onto land patterns on a subsurface layer of the printed circuit structure. However, handling and placing of these small components requires systems with a high level of positional accuracy. Interconnection can be accomplished using either deposited solder paste and reflow processing or applying a conductive polymer material. Due to the extremely small land pattern geometries required for mounting the miniature passive components, companies commonly rely on precision dispensing these materials.

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Embedding Components, Part 4: Passive Component Selection and Land Pattern Development

11-29-2018

As noted in Part 3 of this series, a broad range of discrete passive component elements are candidates for embedding, but the decision to embed these component elements within the multilayer circuit structure must be made early in the design process. While many of these components are easy candidates for integrating into the substrate, others may not be suitable, or they are difficult to rationalize because they involve more complex process methodology.

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Embedding Components, Part 3: Implementing Discrete Passive Devices

11-15-2018

Most of the passive components used in electronics are discrete surface mount components configured to mount onto land patterns furnished on the surface of a PC board. Designers have several choices for providing passive functions in a system design, such as discrete surface-mounted passives, array passives or passive networks, integrated (Rs and Cs) passive devices, and embedded discrete passive components.

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Designers Notebook: Strategies for High-Density PCBs

01-01-2018

As hand-held and portable electronic products and their circuit boards continue to shrink in size, the designer is faced with solving the physical differences between traditional printed board fabrication and what’s commonly referred to as HDI processing. The primary driver for HDI is the increased complexity of the more advanced semiconductor package technology. These differences can be greater than one order of magnitude in interconnection density.

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2017

Strategies for High-Density PCBs

11-27-2017

As hand-held and portable electronic products and their circuit boards continue to shrink in size, the designer is faced with solving the physical differences between traditional printed board fabrication and what’s commonly referred to as high-density interconnect (HDI) processing.

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Embedding Components, Part 2

07-30-2017

Technology and processes for embedding capacitor and inductor elements rely on several unique methodologies. Regarding providing capacitor functions, IPC-4821 defines two methodologies for forming capacitor elements within the PCB structure: laminate-based (copper-dielectric-copper) or planar process and non-laminate process using deposited dielectric materials.

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Embedding Components, Part 1

06-30-2017

The printed circuit has traditionally served as the platform for mounting and interconnecting active and passive components on the outer surfaces. Companies attempting to improve functionality and minimize space are now considering embedding a broad range of these components within the circuit structure. Both uncased active and passive component elements are candidates for embedding but the decision to embed components within the multilayer circuit structure must be made early in the design process.

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2016

Specifying Lead-Free Compatible Surface Finish and Coating for Solderability and Surface Protection

07-06-2016

A majority of the components furnished for electronic assembly are designed for solder attachment to metalized land patterns specifically designed for each device type. Providing a solder process-compatible surface finish on these land patterns is vital...

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Flexible and Rigid-Flex Circuit Design Principles, Part 6

05-26-2016

The designer is generally under pressure to release the documentation and get the flexible circuit into production. There is, however, a great deal at risk. Setting up for medium-to-high volume manufacturing requires significant physical and monetary resources. To avoid potential heat from management, the designer must insist on prototyping the product and a thorough design review prior to release.

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Flexible and Rigid-Flex Circuit Design Principles, Part 5

04-27-2016

The outline profile of the flexible circuit is seldom uniform. One of the primary advantages of the flexible design is that the outline can be sculpted to fit into very oblique shapes. In this column, Vern Solberg focuses on outline planning, physical reinforcement, and accommodating bends and folds in flexible and rigid-flex circuits.

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Flexible and Rigid-Flex Circuit Design Principles, Part 4

03-30-2016

All of the design rules for the glass reinforced-portion of the board (land pattern geometry for mounting surface mount devices, solder mask and the like) are now well-established. One unique facet of fabricating the rigid-flex product is how the flexible portion of the circuit is incorporated with the rigid portion of the circuit. As a general rule for multilayer PCB design, furnish a balanced structure by building up the circuit layers in pairs (4, 6, 8 and so on).

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Flexible and Rigid-Flex Circuit Design Principles, Part 3

03-02-2016

This column focuses on methods for specifying base materials, and also address copper foil variations and fabrication documentation. It is important to research the various products in order to choose the one that best meets the design requirements.

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Flex and Rigid-Flex Circuit Design Principles, Part 2

02-19-2016

Flexible circuits are commonly developed to replace ordinary printed circuit board assemblies that rely on connectors and hardwire for interconnect.

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Flex and Rigid-Flex Circuit Design Principles, Part 1

01-27-2016

Flexible circuits represent an advanced approach to total electronics packaging, typically occupying a niche that replaces ordinary printed circuit board assemblies and the hard-wire interface needed to join assemblies.

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2005

PCB Designers Notebook: Flexible Circuit Design

01-03-2005

The flexible circuit was originally used as a conductive element for interfacing signals from one electronics assembly to another.

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