Designers Notebook: Design for Test, Part 3

The general trend in electronics is to improve performance and minimize product size, often leading to more complex printed circuit boards and higher component density. Semiconductor packages in particular have become more complex, with many having multiple functions interconnected within the package or onto the silicon itself. For products with very high component density, companies soon realize that 100% test-probe access may not be possible. For example:

  • A significant number of circuit boards include components assembled onto both sides, limiting access for physical probing
  • It is impossible to probe the terminals of the very fine-pitch array configured components to identify functional or assembly process-related defects
  • Very high density, small-size circuit boards do not always have accessible test lands, making it challenging to probe suspected nodes

Programmable logic devices (PLDs) and flash memory devices, for example, are often supplied in array packaging and soldered directly onto the circuit board. When a design includes programmable devices from multiple sources, the user must often rely on different software variations for programming these devices.

The focus of Part 1 and Part 2 of this “Design for Test” series was on bare-board testing and fixed-probe assembly test. Information gathered for Part 3 furnishes the designer with an overview of preparing for boundary scan testing, an integrated method for testing interconnects on populated printed circuit boards.

Electrically testing assembled circuit boards in a high-volume production environment requires a significant amount of engineering resources to develop the fixtures and programming required for in-circuit testing. Increasingly, the more complex semiconductor devices feature bus technology, enabling the potential to rapidly access thousands of test nodes for evaluating each component’s function and interconnection integrity.

Network access can be made from board edge contactors or by surface probe contact to a few designated semiconductor terminals. This is an extremely thorough test method, enabling both in-circuit test coverage and system diagnostics. Implementing boundary scan negates the need for the traditional ICT “one node per net” requirement (at least on the devices furnished with self-test capability).

JTAG Test per IEEE 1149.1
Joint Test Action Group (JTAG) is a team of test engineering specialists that developed a standard procedure for verifying designs and testing complex circuit board assemblies. Although the process requires that unique test programs be generated before use, the programming provides a cost-effective method for testing products having restricted surface area for probe interface. This boundary-scan test architecture offers the capability to efficiently test high-terminal-density core logic components, capturing functional data while the device(s) operate normally. Boundary-scan cells built into each device capture data from core logic signals. This captured data is then serially shifted out and externally compared to projected results (Figure 1).

Vern_April_Fig1_cap.jpg
Boundary scan testing can identify structural fault locations, even beneath array-configured semiconductor packaging, without requiring physical access to all nodes on the circuit board. In a typical boundary scan test, the tester sends diagnostic signals to the device’s data input pin. The boundary-scan cells capture the signals and serially shift them through the core logic. The output is then serially shifted out of the core through the data output pin.

Test Node Access Requirements
The JTAG boundary scan test technique uses a shift register latch cell built into each external connection of every boundary scan compatible device. One boundary scan cell is contained in the integrated circuit line adjacent to each I/O pin or terminal, and when used in the shift register mode it can transfer data along to the next cell in the device. There are defined entry and exit points for the data to enter and exit the device, and it is therefore possible to progressively link several devices together.

The test equipment typical of that developed by JTAG Technologies (Figure 2) offer maximum flexibility and independence and can be set up as a stand-alone boundary-scan station integrated or combined with functional test and in-circuit test (ICT) or when using flying probe testers (FPT).

Vern_April_Fig2_cap.jpgThere are several control and data lines that form the test access port. These lines, known as test clock and test mode select, as well as an optional test reset line, are connected in parallel to the semiconductors in the boundary scan chain. Connections designated test data input and test data output are daisy-chained together to provide a path around the boundary scan enabled devices. Functional data is sent into the test data input node of the first semiconductor. Output from the first device is next connected to test data input of the next device(s).

Boundary scan implementation benefits include:

  • Accelerate new product development
  • Reduced time-to-market
  • Fast and efficient test program generation
  • Ideal for boards undergoing design revisions

The JTAG test procedure is highly versatile and will be used across the circuit board assembly production process for design verification, in-system programming, testing, and debugging procedures. Boundary scan testing will rely on built-in component test functions, typically accessing four to six terminals of the semiconductor package as noted above. These terminals enable full analysis of the device. Fault detection is achieved by exploiting test-enabled components on the PCB which, in addition to their normal functionality, provide special test logic that scans through the serial JTAG interface.

X-JTAG has been working with a variety of test solution providers, including flying probe test system providers, to offer the best-in-class test capability and value for users. Ensuring continuous design for test improvement, and that testing ball grid array (BGA) devices on dense boards does not affect test coverage in, will require combining JTAG boundary scan and bed-of-nails with high-speed flying probe test systems (Figure 3) to achieve the absolute best results.

Vern_April_Fig3_cap.jpg

Powerful and easy to use, integrated testing enables engineers to minimize test time while maximizing test coverage.

Documentation Transfer for Assembly Test
The test program engineering specialist will require the netlist for the specific circuit board designated for testing, and will include boundary scan description language files for the boundary scan for all components contained within the circuit. With this information it is possible for the test program engineer to create the test patterns used to accomplish the test. This data allows the system to detect and isolate any faults for all boundary-scan testable nets within the circuit. It is also possible for the test program developer to create test vectors that enable the system to detect faults on the nodes or pins for non-boundary scan components that are surrounded by boundary scan devices.

While requirements may vary, most documents required for setting up assembly test are quite standard to the industry. These include:

  • Assembly detail: This will include graphics representing component outline, location, and reference designators for each device mounted on the board surface
  • Electrical schematic diagram: Will furnish interconnect detail between all passive and active components mounted on the board’s surface with corresponding reference designators
  • Circuit board fabrication detail: Will include the primary mechanical outline dimensions, tooling locations, materials specified for fabrication, and circuit layer sequence with a representative cross-section detail
  • CAD file: The digital data developed for component placement and circuit interconnect will furnish specific X-Y component coordinates, component orientation, and features provided for test probe access
  • Gerber file: The Gerber file is a standard vehicle developed for PCB design data storage or transfer of PCB circuit image for each layer of the board and includes solder mask and nomenclature images
  • Bill of materials: All components are listed by type, value and/or identifying part number and quantity. For two sided SMT assembly, component types are to be separated and identified by where located
  • Approved vendor list: The vendor list represents the user’s “qualified suppliers” for all materials and components designated for the circuit board assembly
  • Netlist: Identifies the electrical connections (node) between component terminals in the circuit. The list will include component reference designators, component type, and terminal numbers
  • Test node X-Y coordinates
  • : The specific location of each node identified on the netlist must be referenced from a single fiducial target feature chemically etched within the circuit pattern

In addition to the documentation noted above, the circuit board developer will furnish requirements related to the end product’s expected operation or use environment and include key data for all non-standard semiconductors.

Boundary Scan Test Compliance
Prior to releasing the board for fabrication, the designer and/or cognizant engineer responsible for developing the board will review the design with the test program developer to ensure the end-product can be tested effectively. If the design cannot meet full probe access to all nets or boundary scan terminals, the test fixture developer will probably request the addition of any test lands needed to enable the effective probing of all nodes in the network. Doing so may challenge the designer in altering the design to add test probe features, but the change will not likely affect the price of the actual circuit board fabrication. However, it will make a significant difference in achieving 100% testability of the PCB design.

Resources

  1.  JTAG Technologies, Technical support Americas: support@jtag.com.
  2. XJTAG Technologies, “Design for Test Guidelines:” enquiries@xjtag.com.

This column originally appeared in the April 2022 issue of Design007 Magazine.

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2022

Designers Notebook: Design for Test, Part 3

05-04-2022

The general trend in electronics is to improve performance and minimize product size, often leading to more complex printed circuit board and higher component density. Semiconductor packaging in particular, have become more complex, many having multiple functions interconnected within the package or onto the silicon itself. For products with very high component density companies soon realize that 100% test-probe access may not be possible.

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2021

Designers Notebook: Embedding Resistor Elements—Part 2

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2020

Designers Notebook: Panel-level Semiconductor Package Design Challenges

05-15-2020

Semiconductor package specialists continually work to improve high-volume manufacturing process efficiencies while reducing manufacturing costs. A majority of the commercial semiconductors are built-up on the surface of a circular-shaped silicon wafer with metalized terminal features at their perimeter to accommodate wire-bond interface with a lead-frame or package substrate. Vern Solberg explains.

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2019

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2018

Embedding Components, Part 5: Alternative Termination Methodologies and Surface Plating Variations

12-19-2018

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2017

Strategies for High-Density PCBs

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2016

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2005

PCB Designers Notebook: Flexible Circuit Design

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