Beyond Design: Fringing Fields

Electromagnetic energy is all around us from TV to radio and communication waves and the Earth’s magnetic field and plasma shield that protect us from the sun’s solar flares (Figure 1). This activity is driven by the sun’s magnetic field. Like all physical phenomena, they tend to follow the same rules.


Figure 1: The sun’s corona discharge (solar flare) and Earth’s magnetic field.

A parallel plate capacitor (or a planar pair) has two conductors separated by a dielectric layer. Most of the energy in the structure is concentrated directly between the plates. However, some of the energy spills over into the area outside the plates. The electric field lines associated with this effect are called fringing fields. In this month’s column, I will look at how electromagnetic radiation can be emitted from the edges of planes in multilayer PCBs by the fringing fields, possibly causing electromagnetic compatibility (EMC) issues.

Fringing is the bending of the electric flux lines near the edge of the parallel plate capacitors. Fringing is also known as the edge effect. Normally, the flux lines inside the capacitor are uniform and parallel. But at the edges, the flux lines are not straight and bend slightly outward due to the geometry. Also, in a plane pair, signals passing through the cavity may intensify fringing fields (Figure 2).


Figure 2: Signals passing through a plane cavity intensify fringing fields.

When the return current flows through the impedance of a cavity between two planes, it generates voltage. Although quite small (typically in the order of 5 mV), the accumulated noise from simultaneous switching devices can become significant. Unfortunately, as core voltages drop, noise margins become tighter. This voltage, emanating from the vicinity of the signal via, injects a propagating wave into the cavity, which can excite the cavity resonances or any other parallel structure (for instance, between copper pours over planes). Other signal vias, also passing through this cavity, can pick up this transient voltage as crosstalk. And when the wave meets the PCB edge, the two reference planes form a slot antenna and will radiate noise with the potential to generate electromagnetic interference (EMI) to nearby equipment.

The more switching signals that pass through the cavity, the more noise is induced into other signals; it affects vias all over the cavity, not just the ones in close proximity to the aggressor signal vias. This cavity noise propagates as standing waves, spreading across the entire plane pair. This is the primary mechanism by which high-frequency noise is injected into cavities by signals transitioning through cavities, using each plane successively as the signal return path.

Cavity resonance also affects the power/signal return layers at the edges of the PCB. Edge effects can be particularly problematic since it is the board edges that are in such close proximity to the chassis; hence, the radiation fields can induce currents into the chassis frame.

When the cavity has open end boundary conditions, resonances arise when a multiple of half wavelengths can fit between the ends of the cavity. Figure 3 shows the cavity resonance of a plane pair with a resonant frequency of 1 GHz. If the signal clock frequency (or harmonics) are multiples of 1 GHz, then noise can be injected into the plane cavity. When the clock or data harmonics overlap with the cavity resonant frequencies, there is the potential for long-range coupling between any signals that run through the cavity. This is one reason why all return planes should be GND layers so that stitching vias between GND planes can be placed adjacent to each signal via transition to minimize the possibility of exciting the cavity resonance.


Figure 3: Amplitude at the far end of planes as input frequency is swept. (Source: Eric Bogatin)

Cavity resonances are (at first) a signal integrity issue, but the amplification of cavity resonance excited by fast rise time signals at high frequencies can also contribute to electromagnetic emissions. The frequency components of the voltage noise are related to the peak impedance of the cavity and the frequency components of the return currents. In any complex system, with typical interconnect density, avoiding signal layer transitions is not practicable and is an issue that designers must live with. However, one can learn to avoid injecting excessive noise into the cavity or at least minimize the impact.


Figure 4 gives an example of a signal trace on the top microstrip layer routed outside the reference plane area. I see this all the time when I analyze PCBs. The signal path is very close to the edge of the PCB, and the reference planes are not located directly under the trace to provide full field coverage. The electric fields (blue) tend to couple to the plane edges, whereas the magnetic fields (red) radiate outward omnidirectionally. The fringing effect creates a very “hot” area and will radiate and possibly create coupling issues to nearby circuits, cables, and slots in enclosures.

Figure 5 illustrates the cross-section on a microstrip trace, and its associated plane return current distribution (red). Where the electric fields (blue) are more tightly coupled to the plane directly below the trace, the return current also exhibits tighter coupling. But where the field spreads out from the trace, the larger loop area between the signal and the return current path increases the inductance.


Figure 5: Microstrip plane return current distribution.

Return current tends to couple to the signal conductor, falling off in intensity, with the square of increased distance. A stripline (inner layer) return current distribution is narrower with the fields more intense above and below the trace. The electric field spreads out to approximately three times the width of the trace (on both sides), so it is important to ensure there is enough plane coverage to prevent radiation.

To reduce emissions and increase immunity, when routing a PCB, try to avoid positioning critical signals close to the edge of the board. This creates a more robust system for electromagnetic compatibility.

There are various approaches pertaining to reducing radiation edge effects from the PCB. In many cases, energy can be reflected, possibly creating additional internal cavity resonance effects and coupling to internal vias, also resulting in increased radiation. When plane pairs resonate, their emissions come from the fringing fields at the board edges. With ground/power plane pairs, edge-fired emissions can be reduced by reducing the plane separation and lowering the AC impedance. Alternatively, make the power planes slightly smaller (~200 mils) than the GND plane. This modifies the pattern of the fringing fields, pulling them back from the edge, and may help reduce emissions to some extent.

Edge plating, as the name suggests, is the process of plating the edges around the PCB. I first saw this technique used at NEC back in 1994. This is an elegant (but expensive) solution to prevent emissions from extremely high-speed SERDES signals on terabit routers, etc. but is an overkill for a typical high-speed design.

Another way to mitigate this problem is to create a via fence stitched to ground around the perimeter of the PCB. If the spacing between the stitching vias is less than or equal to one-eighth of a wavelength, the via fencing will appear as a short circuit, causing the propagating wave to be reflected back to the source rather than being launched from the PCB edge.

A post-production solution is to employ cavity resonance absorber material applied along the edge of the PCB, which dissipates the edge radiation from the PCB without using additional board real estate. It also reduces the possibility of board resonance problems by dissipating the energy and not reflecting the energy back into the interior of the board. However, it is always best to fix the problem at the source rather than applying as a quick fix after production.


Key Points

  • Fringing is the bending of the electric flux lines near the edge of the parallel plate capacitors.A signal passing through a plane cavity may intensify fringing fields.
  • As core voltages drop, noise margins become tighter.
  • Signals passing through a plane cavity inject propagating waves, which can excite the cavity resonances.
  • When the wave meets the PCB edge, the two reference planes form a slot antenna and will radiate noise.
  • The cavity noise propagates as standing waves spreading across the entire plane pair.
  • When the cavity has open end boundary conditions, resonances arise when a multiple of half wavelengths can fit between the ends of the cavity.
  • Return current tends to couple to the signal conductor, falling off in intensity with the square of increased distance.
  • Avoid positioning critical signals close to the edge of the board.
  • Edge plating is an elegant (but expensive) solution to prevent emissions from extremely high-speed SERDES signals.
  • GND stitching vias are placed at one-eighth of a wavelength as a short circuit, causing the propagating wave to be reflected back to the source.
  • Edge radiation should be eliminated at the source.

Further Reading

This column originally appeared in the October 2020 issue of Design007 Magainze.



Beyond Design: Fringing Fields


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Contrary to common belief, the transmission line does not carry the signal itself but rather guides electromagnetic energy from one point to another. It is the movement of the electromagnetic field or energy, not voltage or current that transfers the signal. The voltage and current exist in the conductor, but only as a consequence of the field being present as it moves past.

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Mythbusting: There are No One-way Trips!


One of the greatest myths in PCB design is that we only have to route signal traces from pin-to-pin to make a complete connection. And, that ensuring these traces have matched delay is the only timing issue we need to consider. However, current is not a one way trip--it must complete the circuit back to the source to provide the round-trip current loop.

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Matched Length Does Not Always Equal Matched Delay


In previous columns, Columnist Barry Olney has discussed matched length routing and how matched length does not necessarily mean matched delay. But, all design rules, specified by chip manufacturers regarding high-speed routing, specify matched length--not matched delay. In this month's column he takes a look at the actual differences between the two.

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Beat the Traffic Jam - Effective Routing of Multiple Loads


In a previous column, Barry Olney discussed various termination strategies and concluded that a series terminator is best for high-speed transmission lines. But, what if there are a number of loads--how should these transmission lines be routed? For perfect transfer of energy and to eliminate reflections, the impedance of the source must equal the impedance of the trace(s) to the load.

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PDN Planning and Capacitor Selection, Part 2


In Part 1 of this column, Barry Olney looked closely at how to choose the right capacitor to lower the AC impedance of the power distribution network (PDN) at a particular frequency. This month he continues from there looking at the one-capacitor-value-per-decade and optimized value approaches.

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Beyond Design: Entanglement - The Holy Grail of High-Speed Design


While high-speed SERDES serial communications seems to currently be at the cutting edge of technology, maybe it will shortly become an antiquated low-speed solution--even speed-of-light fiber optics may become obsolete. This month, Columnist Barry Olney looks at how quantum physics is transforming our world and how it could affect PCB design.

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Beyond Design: Impedance Matching: Terminations


The impedance of the trace is extremely important, as any mismatch along the transmission path will result in a reduction in signal quality and possibly the radiation of noise. Mismatched impedance causes signals to reflect back and forth along the lines, which causes ringing at the load.

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Material Selection for SERDES Design


Many challenges face the engineer and PCB designer working with new technologies. For SERDES--high-speed serial links--loss, in the transmission lines, is a major cause of signal integrity issues. Reducing that loss, in its many forms, is not just a matter of reducing jitter, bit error rate (BER) or inter-symbol interference (ISI).

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Beyond Design: Practical Signal Integrity


"If you are a digital designer, you will eventually have SI problems whether you like it or not. But all is not lost. If you learn to work with these issues, then you will soon become proficient with high-speed design," says columnist Barry Olney.

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Beyond Design: Design for Profit


Design for profit (DFP) is gaining more recognition as it becomes clear that the cost reduction of printed circuit assemblies cannot be controlled by manufacturing engineers alone. The PCB designer now plays a critical role in cost reduction, says columnist Barry Olney.

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Beyond Design: Skewed Again


Differential skew has become a performance limiting issue for high-speed SERDES links. The operation of such links involves significant amounts of signal processing to recover clocks, reduce the effects of high-frequency losses, reduce inter symbol interference, and improve signal-to-noise ratio.

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Beyond Design: Losing a Bit of Memory


No matter what type of memory used in a design, the clock should always have the longest delay. This ensures that the other signals have time to settle before the clock arrives at the device and samples the bus.

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Beyond Design: Electromagnetic Fields, Part 2


In his last column, Barry Olney discussed how magnetic fields revolve around the earth and how these fields are also present in a multilayer board. Part 2 of "Electromagnetic Fields" will look at how the phenomena influence transmission lines and how they can be applied in a BEM field solver.

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Beyond Design: Electromagnetic Fields, Part 1


Our whole world literally revolves around electromagnetic fields. Columnist Barry Olney says much insight into high-speed PCB design can be gained by understanding the behavior of transmission lines and the influence of their associated electromagnetic fields.

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Beyond Design: Postmortem Simulation


Developing the practice of performing a post-mortem analysis on every project facilitates a culture of continuous improvement. This embedded culture of ongoing, positive change is the best way to ensure long-term success according to Barry Olney.

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Beyond Design: Mixed Digital-Analog Technologies


The key to a successful mixed digital-analog design is functional partitioning, understanding the current return path, routing control and management, and using a common ground plane. Barry Olney takes us into the mix this week.

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Beyond Design: Pre-Layout Simulation


Pre-layout simulation allows a designer to identify and eliminate signal integrity, crosstalk and EMC issues early in the design process. This is the most cost-effective way to design a board. Barry Olney explains why in this case, sooner is better than later.

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Beyond Design: Power Distribution Network Planning


The power distribution network (PDN) of a multilayer PCB should distribute low noise and stable power to ICs over the entire board area. Ideally, the AC impedance, between power and ground, should be zero, up to the maximum operating frequency for reliable performance.

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Intro to Board-Level Simulation and the PCB Design Process


Board-level simulation reduces costs by identifying potential problems at the conceptual stage, so that they can easily be avoided, and then catching any further issues during the design process, eliminating the potentially disastrous final-stage changes. By Barry Olney.

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Board-Level Simulation and the Design Process: Plan B - Post-Layout Simulation


Post-layout simulation covers batch mode simulation, which automatically scans nets on an entire PCB, flagging signal integrity, crosstalk and EMC hot spots. While post-layout simulation can be used for disaster recovery, ideally this process is completed during the design process. Barry Olney explains.

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Beyond Design: A New Slant on Matched-Length Routing


This month, Barry Olney discusses the traditional serpentine routing for matched length signals and looks at a potentially desirable alternative, the octagonal spiral pattern, that can be especially useful if real estate is at a premium.

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Beyond Design: Controlling the Beast


In this column, we will tackle the "microstripum crosstalkus radiarta," an insidious little creature more commonly known as microstrip crosstalk radiation. Thriving on the outer layers of PCBs, crosstalk, like fleas on a dog, can't be eliminated completely or forever; the key is learning how to minimize and control it.

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Beyond Design: Embedded Signal Routing


Is radiation actually attenuated when high-speed signals are routed embedded between the planes? There are specific constraints and factors to consider when assessing just how much attenuation we actually get from embedding the high-speed signals between the planes. Barry Olney breaks it all down.

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Beyond Design: The Dumping Ground


By definition, a ground plane in a PCB is a layer of copper that appears to most signals as an infinite ground potential. This month, we discuss best practices for selecting reference planes and routing pairs for high-speed designs on multilayer boards.

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Beyond Design: Controlling Emissions and Improving EMC


Unintended noise can be a formidable enemy, and it is best to totally eliminate, control or attenuate the emissions at the source. Controlling the impedance of the substrate and terminating the transmission line to match the impedance of the respective source and load significantly reduces radiated noise, virtually eliminating the noise at the source.

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PCB Design Techniques for DDR, DDR2 & DDR3, Part 2


This second and final part in a series examining PCB design techniques will look at a comparison of DDR2 and DDR3, DDR3 design guidelines, pre-layout analysis, critical placement, design rules, and post-layout analysis.

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