Practical Modeling of High-Speed Backplane Channels

As Dave Dunham of Molex Corp. likes to say, "When designing high-speed serial links beyond 10 GB/s, everything matters." And part of that everything is accurate modeling of transmission line losses.

Failure to account for conductor roughness can ruin your day, especially if you are trying to push 28 GBaud/s (56 GB/s) PAM-4 signaling down your channel. To ensure first-time success at these speeds, using the right parameters for dielectric and conductor roughness to feed into modern EDA tools is a prerequisite. This is especially true for long backplane channels.

Many EDA tools include the latest and greatest models for conductor surface roughness and wide-band dielectric properties. But obtaining the right parameters to feed the models is always a challenge. So how do we get these parameters?

One way is to follow the design feedback method which involves designing, building and measuring a test coupon. After modeling and tuning various parameters to best fit measured data, Dk, Df  and roughness parameters can be extracted. They are then used in channel modeling software to design the final product.

The benefits of this method are that it is practical and accurate—if you use the exact same material, glass style and copper foil in your final board stack-up. On the down side, a significant amount of expertise and equipment is required to design, build and measure the test coupon, which takes significant amount of time and money.

To read this entire article, which appeared in the October 2017 issue of The PCB Design Magazine, click here.

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2017

Practical Modeling of High-Speed Backplane Channels

11-14-2017

As Dave Dunham of Molex Corp. likes to say, "When designing high-speed serial links beyond 10 GB/s, everything matters." And part of that everything is accurate modeling of transmission line losses. Many EDA tools include the latest and greatest models for conductor surface roughness and wide-band dielectric properties. But obtaining the right parameters to feed the models is always a challenge. So how do we get these parameters?

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Obsessing over Conductor Surface Roughness: What’s the Effect on Dk?

04-12-2017

You know you have an obsession when you are flying six miles over Colorado and you look out the window at the beautiful scenery, and all you can think about is how the rocky mountain topology reminds you of conductor surface roughness! Well, call me obsessed, because that’s exactly what I thought on my way to DesignCon 2017. This year at DesignCon, I presented a paper titled "A Practical Method to Model Effective Permittivity and Phase Delay Due to Conductor Surface Roughness."

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2016

Practical Modeling of High-Speed Backplane Channels

11-14-2017

As Dave Dunham of Molex Corp. likes to say, "When designing high-speed serial links beyond 10 GB/s, everything matters." And part of that everything is accurate modeling of transmission line losses. Many EDA tools include the latest and greatest models for conductor surface roughness and wide-band dielectric properties. But obtaining the right parameters to feed the models is always a challenge. So how do we get these parameters?

View Story

Obsessing over Conductor Surface Roughness: What’s the Effect on Dk?

04-12-2017

You know you have an obsession when you are flying six miles over Colorado and you look out the window at the beautiful scenery, and all you can think about is how the rocky mountain topology reminds you of conductor surface roughness! Well, call me obsessed, because that’s exactly what I thought on my way to DesignCon 2017. This year at DesignCon, I presented a paper titled "A Practical Method to Model Effective Permittivity and Phase Delay Due to Conductor Surface Roughness."

View Story
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2014

Accelerating the SI Learning Curve - Bogatin's SI Academy

08-06-2014

Columnist Bert Simonovich writes, "Last year, Dr. Eric Bogatin, the 'Signal Integrity Evangelist,' announced the end of his famous signal integrity classes. At the time I remember thinking to myself, 'What's next for Eric?' If you know Eric, like I do, you realize that the end of one phase of his career usually means the start of the next one. And now we know what that is."

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Bert's Practical Design Notes: Accelerating the SI Learning Curve - Bogatin's SI Academy

08-06-2014

Columnist Bert Simonovich writes, "Last year, Dr. Eric Bogatin, the 'Signal Integrity Evangelist,' announced the end of his famous signal integrity classes. At the time I remember thinking to myself, 'What's next for Eric?' If you know Eric, like I do, you realize that the end of one phase of his career usually means the start of the next one. And now we know what that is."

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2013

Accelerating the SI Learning Curve - Bogatin's SI Academy

08-06-2014

Columnist Bert Simonovich writes, "Last year, Dr. Eric Bogatin, the 'Signal Integrity Evangelist,' announced the end of his famous signal integrity classes. At the time I remember thinking to myself, 'What's next for Eric?' If you know Eric, like I do, you realize that the end of one phase of his career usually means the start of the next one. And now we know what that is."

View Story

Bert's Practical Design Notes: Accelerating the SI Learning Curve - Bogatin's SI Academy

08-06-2014

Columnist Bert Simonovich writes, "Last year, Dr. Eric Bogatin, the 'Signal Integrity Evangelist,' announced the end of his famous signal integrity classes. At the time I remember thinking to myself, 'What's next for Eric?' If you know Eric, like I do, you realize that the end of one phase of his career usually means the start of the next one. And now we know what that is."

View Story
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2012

Bert's Practical Design Notes: Perils of Lumped Via Modeling

05-30-2012

Popular opinion has held that PCB vias were mainly capacitive in nature, and therefore could be modeled with lumped capacitors. Although this might be true when the rise time of the signal is greater than or equal to 3x the delay of the via discontinuity, I'll show you why it is no longer appropriate to think this way.

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Bert's Practical Design Notes: The "Stubinator" vs. Back-Drilling

04-11-2012

I was intrigued by a DesignCon 2010 paper presented by Dr. Nicholas Biunno on a new matched terminated stub technology developed by Sanmina-SCI Corporation. The company calls this technology MTSvia, and it allows the embedding of metal thin-film or polymer thick-film resistors within a PCB stackup during fabrication. Personally, I like to call this technology the "Stubinator."

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Backplane High-Level Design: The Secret to Success

01-04-2012

In my previous column, I touched briefly on the concept of backplane high-level design (HLD). For any new backplane design, I always recommend starting with a HLD. It helps you capture your thoughts in an organized manner, and later provides the roadmap to follow for detailed design of the backplane. This week, I will touch on key aspects that go into this process.

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2011

Bert's Practical Design Notes: Perils of Lumped Via Modeling

05-30-2012

Popular opinion has held that PCB vias were mainly capacitive in nature, and therefore could be modeled with lumped capacitors. Although this might be true when the rise time of the signal is greater than or equal to 3x the delay of the via discontinuity, I'll show you why it is no longer appropriate to think this way.

View Story

Bert's Practical Design Notes: The "Stubinator" vs. Back-Drilling

04-11-2012

I was intrigued by a DesignCon 2010 paper presented by Dr. Nicholas Biunno on a new matched terminated stub technology developed by Sanmina-SCI Corporation. The company calls this technology MTSvia, and it allows the embedding of metal thin-film or polymer thick-film resistors within a PCB stackup during fabrication. Personally, I like to call this technology the "Stubinator."

View Story

Backplane High-Level Design: The Secret to Success

01-04-2012

In my previous column, I touched briefly on the concept of backplane high-level design (HLD). For any new backplane design, I always recommend starting with a HLD. It helps you capture your thoughts in an organized manner, and later provides the roadmap to follow for detailed design of the backplane. This week, I will touch on key aspects that go into this process.

View Story
Back

2010

Bert's Practical Design Notes: Perils of Lumped Via Modeling

05-30-2012

Popular opinion has held that PCB vias were mainly capacitive in nature, and therefore could be modeled with lumped capacitors. Although this might be true when the rise time of the signal is greater than or equal to 3x the delay of the via discontinuity, I'll show you why it is no longer appropriate to think this way.

View Story

Bert's Practical Design Notes: The "Stubinator" vs. Back-Drilling

04-11-2012

I was intrigued by a DesignCon 2010 paper presented by Dr. Nicholas Biunno on a new matched terminated stub technology developed by Sanmina-SCI Corporation. The company calls this technology MTSvia, and it allows the embedding of metal thin-film or polymer thick-film resistors within a PCB stackup during fabrication. Personally, I like to call this technology the "Stubinator."

View Story

Backplane High-Level Design: The Secret to Success

01-04-2012

In my previous column, I touched briefly on the concept of backplane high-level design (HLD). For any new backplane design, I always recommend starting with a HLD. It helps you capture your thoughts in an organized manner, and later provides the roadmap to follow for detailed design of the backplane. This week, I will touch on key aspects that go into this process.

View Story
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