SMT Solver: Benchmarking Defect Levels in Your Products

In this column, I will discuss why zero defects may be a desirable goal but not a realistic one. I will share some industry data to prove my point, and you can use that data to benchmark defect levels in your products. I will also address the choices we make about selecting components that have a big impact on the level of defects you should expect.

I do want to make one thing clear. It may be unrealistic to have zero defects in products right after reflow, but we do need zero defects in products that we ship to the customer. That is the very basic reason for inspection, test, and repair even though they are non-value-added process steps, but they are necessary steps. After all, you don’t want your customers to discover those defects at their site or in the field.

In next month’s column, I will talk about good and bad defects. Yes, there are bad and not-as-bad defects, even though all defects are unacceptable. Heads up: Almost all companies' products have bad defects. They can escape despite the rigorous test and inspection regimes you may have.

Why Do We Not Have Zero Defects?

Most companies attempt to achieve higher yield in SMT products through trial and error at considerable expense and frustration. Even though we have been manufacturing SMT products in high volume for more than three decades, less than 10% of companies have first-pass yield of more than 90%. That means 90% of companies have much lower first-pass yield.

I am using 1985 as the baseline for high-volume motherboard production. Some of you may remember the first serious PCs with Intel 286—a very fast 6-MHz processor. It cost me US$5,000 with a 20% Intel employee discount. I do acknowledge that I went overboard with two floppy disks and lots of memory (256KB, not MB), but I did save lots of money since I did not pay another $1,600 for 30 MB of hard drive. Why did I need a hard drive when I had a high-density, 1-MB floppy drive? It was more than adequate for writing the first edition of my textbook Surface Mount Technology: Principles and Practice.

On a serious note, the motherboard design and process steps have not changed since then. However, the complexity of newer motherboards has only increased with lower pitch packages that must be processed with some of the same old packages, including through-holes. Use of lead-free materials and no-clean fluxes have compounded the problem.

I will have some defect data later on in this column, but the bottom line is that 90% of companies are doing too much rework. Rework adds to the cost of the product and reduces the reliability of solder joints due to an increase in intermetallic thickness each time the solder joint is reflowed. The reasons for this high defect rate include the following:

  • The processes are at very high speeds
  • Machines must perform them
  • The equipment must be characterized thoroughly, which can be defined as understanding all parameters that affect the equipment’s performance
  • Vendors may say it is easy, but it is not
  • Most large companies have assigned engineers to optimize, and small companies learn as they go
  • Learning as you go is not an option because revenue or product schedules (or both) may be impacted adversely

What Is the Defect Level in the Electronics Industry Today?

Let me start by citing a paper by Stig Oresjo[1]. This is an old paper, but with the widespread use of fine- and ultra-fine-pitch QFP; high-pin-count BGAs; 0402, 0201, and 01005 resistors and capacitors; and lead-free materials and no-clean flux, yield problems are not getting any better. I must also note that the conclusions in this paper are very similar to my own findings at various client sites during my consulting assignments.

Stig Oresjo conducted an extensive study at 15 major U.S. and European Tier 1 OEM and EMS companies. He used over 325,000 boards with over 550 board configurations amounting to over one billion total solder joints. It is safe to say this study used a large sample size and these manufacturers were Tier 1 assemblers who could afford AXI inspection systems costing over $500,000.

Only AXI machines and not functional or in-circuit test (ICT) equipment were used in the study to determine defects. Taking into account the limitations of AXI machines, if anything, the defects counted may have been higher if ICT and functional tests were also used. Be as it may, the defect levels in the study varied between 650 to 10,000 PPM, and the average for all the boards was 1,100 PPM.

You do have to follow the correct procedure for calculating PPM levels. For example, if you have 100 components on your board and all components together have 1,000 leads, the total opportunities for defects are 1,100 (i.e., all components are bad, and all solder joints are bad). Hopefully, you are not that bad and unlucky (no one is) and you only have 11 defects in that product. Your PPM level will be 10,000 (11 divided by 1,100 multiplied by one million).

The beauty of calculating the PPM is that it does not matter how simple or complex your board is. However, while first-pass yield is a valid method for quality measurement, it does not distinguish between a very simple board with 1,000 opportunities for defects and a complex board with 10,000 opportunities for defects. A much lower first-pass yield in a complex board may be a better indicator of quality than a higher first-pass yield in a simpler board. We should use both methods to benchmark our quality level.

Component Types, Pitch, and Defect Levels

It is important to know the relationship between the type of components and the defects levels in them. For example, one of the interesting findings in the study was close relationships between types of components and defects. For example, even though we have almost 70 years of experience in wave soldering through-hole components, they had a very high defect level (4,000 PPM). Compare that to 1,400 PPM for gull-wing devices and only 600 PPM for BGAs. The average of all these components was 1,100 PPM.

Table1_Prasad_Jun2019.jpgTable 1: QFP defect levels vs. pitch.

The biggest impact on defects is the pitch of a component. Pitch is defined as the distance between the centers to the center of adjacent pins, not the distance between adjacent pins. Pitch of a component determines the selection of solder ball powder size, the type of paste, and the kinds of printers and pick-and-place machines you need to process them. For example, the study found that PPM levels varied for different pitches of a gull-wing device. The findings are in Table 1.

It goes without saying: Be careful when using pitches below 20 mils or 0.5 mm.

Targeting Defect Levels in Your Products

I have seen a very low level of defects, such as 6 PPM in one Intel product and 4.5 PPM at one EMS company in Malaysia. However, even at these companies, not every product had such a low defect rate. While less than 50 PPM is very rare, it is not uncommon or impossible to have less than 100 PPM. However, as highlighted in my May 2019 column, you need to not only have in-house written DFM and process documents but also (and more importantly) follow them.

Also, as mentioned earlier in this column, some components, such as through-hole for wave soldering and gull-wing components with pitches below 0.5 mm, will make it harder to achieve lower PPM levels. Use such components only when you don’t have other options.

Achieving the low PPM defect level is important but not sufficient for high yield and reliability. You need to have the right kind of defect, which will be the subject of my next column in July. Stay tuned; it’s only one month away.

Ray Prasad is the president of Ray Prasad Consultancy Group and author of the textbook Surface Mount Technology: Principles and Practice. Prasad is also an inductee to the IPC Hall of Fame—the highest honor in the electronics industry—and has decades of experience in all areas of SMT, including his leadership roles implementing SMT at Boeing and Intel; helping OEM and EMS clients across the globe set up strong, internal, self-sustaining SMT infrastructure; and teaching on-site, in-depth SMT classes.

This article was originally published in the June 2019 issue of SMT007 Magazine.



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