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He explained the three-way relationship between ESA and its PCB and equipment manufacturers, with standardisation driven by ECSS, the European Cooperation for Space Standardization, and harmonisation, technology roadmapping and R&D facilitated by a PCB/SMT working group of space agencies, qualified PCB manufacturers and leading European OEMs. The qualification and audit process for PCB suppliers was specified in ECSS-Q-ST-70-10, which defined the requirements imposed on the customer, the supplier and the qualified PCB manufacturer for PCB procurement.
PCBs were seen as the platform for placement and routing for complex components, and needed to be comparable to components in terms of reliability and complexity, but for a much lower cost, for example a PCB could cost 2000 euro, whereas an area array device could cost ten times as much. PCB design was driven by increasing pin count, miniaturisation and signal integrity requirements, resulting in complex, dense and short conductor routing. PCB material selection was driven more by assembly and repair considerations than by the operational environment in space, and PCB build-up was driven by more by capability and miniaturisation than by manufacturability. But material, build-up and metallisation processes affected the reliability of interconnections and insulation, and design and manufacturability were key factors.
Heltzel discussed latent short circuit failure mechanisms resulting from contamination, and how the risks could be mitigated in design, manufacture and base material supply. Cleanliness was critical not only in PCB fabrication but also in laminate manufacture, and the ballot on the adoption of the draft Appendix A to IPC-4101 was imminent. Open circuit failure in the PCB could be caused by broken metallisation as a result of thermal excursions during assembly or in a space environment, and the assembled PCB was susceptible to mechanical stress and CTE mis-match with components. Interconnection Stress Testing (IST) had been introduced as a means of quickly quantifying the robustness of a PCB, and was very much more sensitive than microsectioning alone, although the correlation remained to be verified specifically for space applications. The working group for the revision of ECSS-Q-ST-70-10 aimed to include IST testing in the new ECSS-Q-ST-70-60 “PCB qualification and procurement,” by the end of 2016.
The following two papers were presented consecutively by Emma Hudson, UL’s Industry Lead for PCBs in Europe, Latin America, the Middle East and Africa. The first was a review of developments in safety standards for PCBs and related materials, which included the FR-4 update, latest revisions of the Production Board Certification Option, and current Standards Technical Panel proposals for a new FR-15 laminate ANSI grade, new UL/ANSI grades CEM-3, and standardised pre-conditions for solder limit evaluations.
Traditional FR-4 laminates, based on brominated epoxy resin, had evolved to meet market needs for improved reliability and higher electrical performance, and to satisfy environmental legislation. The new UL/ANSI types replacing FR-4 in UL 746E were brominated, designated FR-4.0, or non-halogen, designated FR-4.1, with a maximum of 45% of inorganic fillers. All FR-4 laminates had to be re-categorised by 30th June 2016, after which “FR-4” would no longer be a valid UL/ANSI category. Progress on solder resists being recognized for use on FR-4.1 had been slow and this was impacting the amount of testing needed for many PCB manufacturers.
In the recently published revision to UL 796, there was a new option to gain safety certification through the testing of the actual production board in lieu of a representative sample, which would benefit quick-turn production, although the PCB type would be limited by the production construction tested.
There was a new standard proposal for a higher-performance FR-4-type material designation: ANSI Grade FR-15, a 150°C relative thermal index (RTI) laminate with the same resin and reinforcement material as FR-4. FR-15.0 material would be based on brominated epoxy with woven glass, and FR-15.1 on non-halogenated epoxy with woven glass. 30 materials showed at least 150°C RTI based on long term thermal aging (LTTA) data. A new UL/ANSI material grade had been requested by OEMs for PCBs used in power supplies, which typically needed a 150°C maximum operating temperature.
Another new standard proposal had been made for new UL/ANSI grades of CEM-3 material, with CEM-3.0 having a brominated resin system the same as traditional CEM-3, CEM-3.1 a halogen-free system similar to traditional CEM-3, CEM-3.2 a brominated system with 130°C RTI and CEM-3.3 halogen-free systems with 130°C RTI.
A task group was currently evaluating solder limits for laminates and PCBs, to reflect maximum temperatures and times in the assembly soldering process. Historically, UL had followed industry practice of simulating assembly with a solder float test, but this was no longer representative in surface-mount assembly so UL had investigated the effect of surface mount reflow on PCB and material degradation, and the STP Solder Limit Task Group had proposed standardised pre-conditions for solder limit evaluations to reduce testing, with profiles standardized by IPC that focused on maximum temperature and time.
Ms. Hudson then moved on to discuss UL’s IST Baseline Performance Programme, the objectives of which were to enable vendor pre-qualification, technology and material characterisation, lot conformance, process and plating monitoring, and trouble-shooting. IST was becoming industry-standard for measuring PCB performance, and standardised designs, protocols and performance criteria had been developed. UL was now offering IST test services in partnership with PWB Interconnect Solutions to meet growing volume demand, and Ms. Hudson made it very clear that there was no relationship between performance testing and safety certification conducted by UL, so that a failure in a performance test would have no bearing on a customer’s UL safety certification. IST test requirements were driven by the OEM and ODM, and each industry sector had its own specific product life cycles, so representative test criteria were critical. There were already a standardized automotive test vehicle and a standardized HDPUG test vehicle. And there was a global price for IST testing, whether the testing was conducted by UL or PWB Interconnect Solutions. UL currently had equipment in Taipei and Fremont (CA) laboratories and planned to install equipment in the UK in the near future.
Emma Hudson having introduced the topic of interconnection stress testing, it was natural that Bill Birch should take up the running, with an update on progress in IST testing, with an outlook toward future HDI and embedded applications. He reflected upon his many years in PCB fabrication: “To understand how they break, you have to understand how they are made!” and commented that he was frequently approached by people who wanted to know why things didn’t work. The concept of measuring changes in resistance under power cycling had begun in Nortel in the 1980s, and IST technology had begun in DEC in the 1990s, with the principle of rapid measurement through every thermal cycle, tracking the thermal cycling profile, measuring the resistance and stopping the test at 10% change in resistance so that the point of failure could be located and the failure mechanism identified. Lead-free legislation had resulted in increased thermal stresses and consequently the importance of effective testing for barrel cracking, and HDI had introduced an additional failure mechanism - interfacial failure of the base of the microvia from the target pad.
He now had 190 IST machines in the field, and PWB Interconnect Solutions was the prime test laboratory for iNEMI and HDPUG, with standardised IST designs and CAF capability. Now its partnership with UL would provide a standardised IST test service. Birch saw the made-for-China sector as a large market opportunity. In addition to IST, PWB Interconnect Solutions offered a non-destructive test for cohesive de-lamination, DELAM. “Most people have it, but don’t know it. We can find it.”
It has become customary for the first day of the conference to conclude with a visit to a local place of special technical interest. This year, two coach-loads of delegates had the opportunity to experience a trip on the Falkirk Wheel, the only rotating boat lift of its kind in the world. Connecting the Forth and Clyde Canal with the Union Canal, the wheel raises boats through a height of 24 metres and is so accurately balanced that only 1.5 kilowatt-hours of power are consumed during each operation. This extraordinary example of innovative engineering was opened in 2002 by Queen Elizabeth II as part of her Golden Jubilee celebrations. And a short diversion on the return journey took delegates to The Kelpies, a monument to horse-powered heritage across Scotland: two 30-metre high horse-head sculptures, opened to the public in 2014 and standing next to a new extension to the Forth and Clyde Canal, forming a gateway at its eastern entrance.
It was perhaps logical that a conference in Edinburgh should include a taste of Scotland’s national drink, so on their return to the city in the evening, delegates were welcomed to the Scotch Whisky Experience at the top of Edinburgh's Royal Mile, which houses a priceless collection of 3,384 bottles of Scotch whisky. And traditions were upheld at the conference dinner where, heralded by the Pipe Major, the haggis was expertly addressed by Alun Morgan in a well-practised Rabbie Burns accent “Fair fa' your honest, sonsie face, Great chieftain o the puddin'-race!”—all eight verses! A memorable evening for all: Slàinte mhath!
I am grateful to Alun Morgan and Walt Custer for allowing me to use their photographs.
Click here for the slide show of the event.