Verific, DARPA Partner to Streamline Access to SystemVerilog EDA Software
December 18, 2020 | Globe NewswireEstimated reading time: 1 minute
Verific Design Automation has announced a partnership agreement with the U.S. Defense Advanced Research Projects Agency (DARPA) to provide the DARPA community access to its electronic design automation (EDA) software in production and development use throughout the semiconductor industry.
Driven by the DARPA Electronics Resurgence Initiative (ERI) to forge collaborations among commercial electronics companies, the agreement offers the DARPA community use of Verific’s hardware description language (HDL) software for the duration of their programs.
“Our support of academic use over the years has been on an ad-hoc basis,” remarks Michiel Ligthart, president and chief operating officer of Verific. “This agreement provides DARPA-funded programs easy and streamlined access to our industry-standard SystemVerilog parsers and elaborators, cracking open ways to meet DARPA’s goal to innovate a fourth wave of electronics progress.”
Specific tools covered under the agreement are Verific's SystemVerilog parser and static and register transfer logic (RTL) elaborators, already serving as front-end for simulation, formal verification, synthesis, emulation, virtual prototyping, in-circuit debug and design for test applications worldwide. For years, Verific's Parser Platforms have given engineering groups a way to eliminate costly internal development of front-end EDA software, accelerating time to market with improved quality.
Currently, more than 20 DARPA-funded programs promote U.S. microelectronics leadership, including some using low-cost, predictably priced tools such as Verific’s software. “DARPA’s programs within the Microsystems Technology Office (MTO) are a bold accelerator of several technical and economic trends in the microelectronics sector,” says Serge Leef, who leads design automation and secure hardware programs. “Giving DARPA’s community easy access to proven, industrial-strength, best-in-class software frameworks enables the researchers to tightly focus on scientific advances while improving the path to a smooth transition of their breakthrough discoveries into commercial and defense applications.”
Verific’s SystemVerilog, VHDL and universal power format (UPF) Parser Platforms are in production and development flows at semiconductor companies worldwide, from emerging companies to established Fortune 500 vendors. Verific distributes its Parser Platforms as C++ source code and compiles on all 32- and 64-bit Unix, Linux, Mac OS and Windows operating systems.
Suggested Items
Synopsys, Samsung Electronics Collaborate to Achieve First Production Tapeout of Flagship Mobile CPU
05/03/2024 | PRNewswireSynopsys, Inc. announced that Samsung Electronics has achieved successful production tapeout for its high-performance mobile SoC design, including flagship CPUs and GPUs, with 300MHz higher performance using Synopsys.ai™ full stack AI-driven EDA suite and a broad portfolio of Synopsys IP on Samsung Foundry's latest Gate-All-Around (GAA) process technologies.
Altair Acquires Research in Flight, Forging a New Path for Aerodynamic Analysis
05/03/2024 | AltairAltair a global leader in computational intelligence, announced it has acquired Research in Flight, maker of FlightStream®, which provides computational fluid dynamics (CFD) software with a large footprint in the aerospace and defense sector and a growing presence in marine, energy, turbomachinery, and automotive applications.
Real Time with… IPC APEX EXPO 2024: Software Solutions for Circuit Board Challenges
05/03/2024 | Real Time with...IPC APEX EXPONolan Johnson speaks with Will Webb from Aster Technologies about their software solutions for design teams, manufacturing, test engineers, and process engineers. Aster's software addresses the increasing complexities of circuit boards and the need for alternative testing methods.
Real Time with… IPC APEX EXPO 2024: My Role as a Technology Solutions Director
05/02/2024 | Real Time with...IPC APEX EXPOPeter Tranitz, senior director of technology solutions at IPC, shares insights into his role as the design initiative lead. He details his advocacy work, industry support, and the responsibilities of the design initiative committee. The conversation also covers the revamping of standards, the IPC Design Competition, and the implementation of design rules in software tools.
Real Time with… IPC APEX EXPO 2024: Ventec Discusses New Pro-bond Family of Advanced Products
05/01/2024 | Real Time with...IPC APEX EXPOChris Hanson, Ventec's Global Head of IMS Technology, outlines the launch of four pro-bond formulas that deliver an outstanding combination of low dissipation factor (Df) with a dielectric constant (Dk) range to maximize the design window for critical PCB parameters. As Chris points out, Pro-bond is designed for low-loss, high-speed applications, while thermal-bond dissipates heat from a component through the board to a heat sink.